Advanced Logic Gates and Circuit Design Revision Notes | A Level AQA Physics

1. Why Logic Gates Matter

Every decision a computer makes — from checking a password to triggering a car's airbag — comes down to combinations of logic gates. These tiny circuits ask yes/no questions about electrical signals and route the answer onward.

At A level, you need to do two things with logic gates: read a circuit and work out what it does, and read a truth table and design the circuit that produces it. Both skills appear regularly in AQA exam questions, so this lesson builds both from the ground up.

2. The Six Gates — What Each One Does

Picture a logic gate as a decision box. Binary inputs enter on the left (each is either 0 or 1), and a single output leaves on the right. The gate's rule determines that output. There are six gates you must know for AQA A level.

The NOT gate is the foundation. Every NAND and NOR gate contains an inversion step, so understanding NOT first makes the others click into place.

Notice the pattern: NAND is AND with the output inverted, and NOR is OR with the output inverted. The small circle on the output symbol in circuit diagrams always signals that inversion. Spotting that circle quickly is a real time-saver in the exam.

The EOR (Exclusive OR) gate deserves special attention because it is the one students most often confuse with OR. An OR gate outputs 1 when both inputs are 1 (among other cases); an EOR gate outputs 0 in that same situation. The word 'exclusive' means it excludes the case where both inputs are high.

3. Full Truth Tables for All Six Gates

A truth table lists every possible input combination systematically. For two inputs A and B, there are four combinations: 00, 01, 10, 11. Writing them in binary counting order (00 → 01 → 10 → 11) guarantees you never miss a row — a habit worth forming now.

Scan the NAND column: it is the exact complement of the AND column. Scan NOR: it is the exact complement of OR. That complementary relationship is not a coincidence — it is the definition of those gates, and it is a quick self-check when you fill in a truth table under exam pressure.

4. Combining Gates — Reading a Circuit

Real circuits chain gates together so that the output of one gate feeds into the input of the next. To find the final output, work left to right: calculate each intermediate output in turn, then feed those values into the next gate.

Think of it like a relay race — each gate passes its result to the next. The trick is to label every intermediate wire with its own column in your truth table. Students who skip intermediate columns almost always make errors on the final output.

Worked example: Tracing a Two-Gate Combination Circuit

A circuit has inputs A and B. Gate 1 is a NAND gate with inputs A and B, producing output P. Gate 2 is a NOT gate with input P, producing final output Q. Complete the truth table and identify what overall gate this combination is equivalent to.

1. A=0,B=0 | A=0,B=1 | A=1,B=0 | A=1,B=1 — Four rows for two inputs. Always write them in binary counting order to avoid missing a combination.
2. NAND rule: output = 0 only when both inputs = 1, otherwise output = 1. A=0,B=0 → P=1 A=0,B=1 → P=1 A=1,B=0 → P=1 A=1,B=1 → P=0 — NAND is AND inverted. The only row where AND gives 1 is A=1, B=1, so NAND gives 0 there and 1 everywhere else.
3. NOT rule: invert P. P=1 → Q=0 P=1 → Q=0 P=1 → Q=0 P=0 → Q=1 — The NOT gate flips every P value. Notice Q is now 1 only when A=1 AND B=1.
4. Q column: 0, 0, 0, 1 AND column: 0, 0, 0, 1 They are identical. — NAND followed by NOT produces the same truth table as a single AND gate. Inverting twice restores the original AND behaviour.

Answer: The combination of NAND → NOT is equivalent to an AND gate. Output Q = $A \cdot B$.

That result — NAND followed by NOT equals AND — is a useful circuit identity. More broadly, any standard two-input gate followed by a NOT gate on its output produces the complemented version of that gate (e.g. AND→NAND, OR→NOR). Recognising these patterns speeds up both circuit analysis and circuit design questions.

5. Constructing a Circuit from a Truth Table

This is the design direction: you are given the desired output column and must work backwards to find a gate combination that produces it. The standard method is the Sum of Products (SOP) approach — a systematic technique that always works.

Here is the core idea. Every row where the output is 1 can be expressed as an AND combination of the inputs for that row. You then OR all those AND terms together. The resulting expression can be directly wired as a circuit.

Worked example: Deducing a Logic Circuit from a Truth Table

Design a logic circuit for the following truth table: A=0,B=0 → Q=0 A=0,B=1 → Q=1 A=1,B=0 → Q=0 A=1,B=1 → Q=1 Identify the gate combination and the simplest equivalent single gate.

1. Row 2: A=0, B=1 → Q=1 Row 4: A=1, B=1 → Q=1 — These are the only two rows we need to account for. Every Q=0 row can be ignored in the SOP method.
2. Row 2 (A=0, B=1): A is 0, so use $\overline{A}$; B is 1, so use B. Term = $\overline{A} \cdot B$ Row 4 (A=1, B=1): A is 1, so use A; B is 1, so use B. Term = $A \cdot B$ — When an input is 0 in a Q=1 row, use its complement (NOT version). When it is 1, use it directly. This ensures the AND term is 1 only for that specific input combination.
3. $Q = (\overline{A} \cdot B) + (A \cdot B)$ — The OR combines both conditions: Q is 1 if either term is 1, which matches the truth table.
4. $Q = (\overline{A} \cdot B) + (A \cdot B) = B \cdot (\overline{A} + A) = B \cdot 1 = B$ — Factor out B. Since $\overline{A} + A = 1$ always (a variable OR its complement is always 1), the expression reduces to Q = B. This is a significant simplification.
5. Q = B: when B=0, Q=0; when B=1, Q=1. Check all rows: (0,0)→0 ✓, (0,1)→1 ✓, (1,0)→0 ✓, (1,1)→1 ✓ — Always verify your simplified expression against every row of the original truth table. One mismatch means the simplification went wrong.

Answer: The circuit requires no gates at all — Q = B directly. The output follows input B regardless of input A.

Not every truth table simplifies that neatly, but the SOP method always gives a working circuit even without simplification. In the exam, if you cannot simplify, draw the unsimplified SOP circuit — it still earns full marks for a correct circuit.

6. A Three-Input Circuit Design — Worked Example

Three-input circuits appear frequently in AQA questions. The method is identical to two-input circuits, but there are now eight rows (2³ = 8) to consider. Systematic row-writing becomes even more important here.

Worked example: Designing a Three-Input Logic Circuit

Design a logic circuit that outputs Q = 1 only when A = 1, B = 0, and C = 1, or when A = 1, B = 1, and C = 1. All other input combinations give Q = 0.

1. A=0,B=0,C=0 → Q=0 A=0,B=0,C=1 → Q=0 A=0,B=1,C=0 → Q=0 A=0,B=1,C=1 → Q=0 A=1,B=0,C=0 → Q=0 A=1,B=0,C=1 → Q=1 A=1,B=1,C=0 → Q=0 A=1,B=1,C=1 → Q=1 — Eight rows for three inputs. Writing them in binary counting order (000 to 111) ensures none are missed.
2. Row 6: A=1, B=0, C=1 Row 8: A=1, B=1, C=1 — Only two rows produce Q=1. Both have A=1 and C=1; they differ only in B.
3. Row 6 (A=1, B=0, C=1): $A \cdot \overline{B} \cdot C$ Row 8 (A=1, B=1, C=1): $A \cdot B \cdot C$ — B=0 in row 6, so use $\overline{B}$. All other inputs are 1, so use them directly.
4. $Q = (A \cdot \overline{B} \cdot C) + (A \cdot B \cdot C)$ — OR the two AND terms together.
5. $Q = A \cdot C \cdot (\overline{B} + B) = A \cdot C \cdot 1 = A \cdot C$ — Factor out A and C. Since $\overline{B} + B = 1$, the B terms cancel. The circuit simplifies to a single AND gate with inputs A and C.
6. Q=1 requires A=1 AND C=1. Row 6: A=1, C=1 → Q=1 ✓ Row 8: A=1, C=1 → Q=1 ✓ All other rows have A=0 or C=0 → Q=0 ✓ — All eight rows match. The simplification is confirmed correct.

Answer: The circuit is a single AND gate with inputs A and C. Input B has no effect on the output. Boolean expression: $Q = A \cdot C$.

The simplification step is not always required in the exam, but it demonstrates deeper understanding and can earn additional marks when a question asks you to 'suggest a simpler circuit'. Always check whether two Q=1 rows differ in exactly one input — that is the signal that a variable will cancel.

7. Exam Technique and Common Mistakes

Logic gate questions follow predictable patterns in AQA papers. The most common formats are: trace a given circuit to complete a truth table, design a circuit from a truth table, and identify which gate a circuit is equivalent to. Each has a reliable method — and each has a trap that catches unprepared students.

One final point on exam language: when a question asks you to 'describe' the operation of a gate, give a sequential account of what happens for each input state without using the word 'because'. When it asks you to 'explain', you must include the reason — link the input condition to the gate rule to the output.

Mastering these six gates — their truth tables, their Boolean expressions, and the SOP design method — covers both specification requirements fully. Every logic circuit question on the AQA paper is a variation of either 'trace this circuit' or 'design a circuit for this truth table', and both are now within your reach.