Modulo-n Counters and Gate Building Blocks Revision Notes | A Level AQA Physics

1. Why Modulo-n Counters Matter

Picture a set of traffic lights that must cycle through exactly four phases before repeating. The electronics driving those lights need a counter that resets after four steps — not after eight or sixteen. That is precisely what a modulo-n counter does: it counts up to a chosen number, then snaps back to zero.

A standard binary counter keeps doubling its range with each extra flip-flop: one flip-flop gives modulo-2, two give modulo-4, three give modulo-8, and so on — always a power of two. Real systems rarely need exactly a power-of-two count. The modulo-n technique lets you pick any count value, which is why it appears throughout timing circuits, frequency dividers, and display drivers.

2. Logic Gates as Building Blocks

Before building a modulo-n counter, you need a firm grip on the gates that will drive the reset pin. The AQA specification is clear on this: you treat each gate as a functional building block. You need to know what a gate does — its truth table and Boolean behaviour — but you do not need to know the transistor-level circuit inside it.

Think of each gate the way you think of a function on a calculator: you know that pressing the square-root button gives you the square root, and that knowledge is enough to use it correctly. The same principle applies here — understand the input-output relationship, and you can combine gates to build any logic function you need.

For modulo-n counter design, AND and NAND gates do the heaviest lifting. You will see why in the next section, once the reset mechanism is clear.

3. How a Basic Binary Counter Works

A binary counter is built from a chain of flip-flops, each one representing one bit of the count. On every rising edge of the clock signal, the count increments by one. With three flip-flops labelled $Q_2$, $Q_1$, $Q_0$ (most significant to least significant), the counter sequences through the binary values 000, 001, 010, 011, 100, 101, 110, 111 — that is, decimal 0 through 7 — before rolling over to 000 again. This is a modulo-8 counter by default.

The outputs $Q_2$, $Q_1$, $Q_0$ are available as separate logic signals. This is the key insight: you can read those signals at any moment and use combinational logic to detect when the count has reached a particular value. That detection signal can then be routed to the counter's reset pin.

Most counter ICs have an active-LOW reset: the counter resets when the reset pin is pulled to logic 0. This means the gate driving the reset pin must output a LOW at the target count. A NAND gate is therefore a natural choice — it outputs LOW only when all its inputs are HIGH, which is exactly when the target count bits are all 1.

4. Building a Modulo-n Counter: The Reset Mechanism

Here is where the two ideas — the binary counter and the gate building blocks — come together. To make a modulo-n counter, you connect the counter's bit outputs to a logic gate whose output drives the reset pin. The gate is wired so that it produces the active reset signal at the instant the count reaches n, forcing the counter immediately back to zero.

The counter therefore never actually stays at count n — it reaches n, the gate fires, and the reset returns the count to zero so fast that n appears only as a transient glitch. The effective sequence is 0, 1, 2,..., n-1, 0, 1, 2,... giving exactly n states. That is the definition of modulo-n behaviour.

Choosing which bits to connect to the gate requires you to express n in binary and identify which bits are 1 in that binary representation. Those are the bits you feed into the AND (or NAND) gate. Bits that are 0 in the binary representation of n do not need to be connected — they will naturally be 0 at count n, so they do not contribute to the detection condition.

Worked example: Designing a Modulo-6 Counter from a 3-bit Binary Counter

A 3-bit binary counter has outputs $Q_2$, $Q_1$, $Q_0$. Design the gate logic needed to make it count modulo-6 (states 0 through 5, resetting on reaching 6). The reset pin is active-LOW.

1. $6_{10} = 110_2$, so $Q_2 = 1$, $Q_1 = 1$, $Q_0 = 0$ — You need to detect when the counter reaches 6. Express 6 in binary to see which output bits will be HIGH at that moment.
2. $Q_2 = 1$ and $Q_1 = 1$; $Q_0 = 0$ — Only the bits that are 1 in the binary representation need to be detected. $Q_0$ is 0 at count 6, so it does not need to be included in the gate inputs — connecting it would prevent the gate from triggering correctly.
3. Use a 2-input NAND gate with inputs $Q_2$ and $Q_1$ — A NAND gate outputs LOW only when all inputs are HIGH. Since the reset pin is active-LOW, a LOW from the NAND gate at count 6 (when $Q_2 = 1$ and $Q_1 = 1$) will trigger the reset. An AND gate followed by a NOT would achieve the same result, but a single NAND gate is more efficient.
4. Check counts 0-5: at count 4 (100), $Q_2=1$ but $Q_1=0$ so NAND output = HIGH (no reset). At count 5 (101), $Q_2=1$, $Q_1=0$ so NAND output = HIGH (no reset). At count 6 (110), $Q_2=1$, $Q_1=1$ so NAND output = LOW (reset triggered). — This verification step is critical. You must confirm the gate does not accidentally fire at an earlier count. Here, no count from 0 to 5 has both $Q_2$ and $Q_1$ simultaneously HIGH, so the reset is unique to count 6.
5. Sequence: 0 → 1 → 2 → 3 → 4 → 5 → (6 triggers reset) → 0 → 1 →... — The counter cycles through exactly 6 states (0 to 5), making it a modulo-6 counter. Count 6 is a transient state that causes an immediate reset and is not held.

Answer: Connect $Q_2$ and $Q_1$ to a 2-input NAND gate; connect the NAND output to the active-LOW reset pin. The counter sequences through states 0–5 and resets on reaching 6.

Notice that the design process has a clear structure: convert n to binary, identify the HIGH bits, feed those bits into a NAND gate (for active-LOW reset) or an AND gate (for active-HIGH reset), and connect the gate output to the reset pin. That four-step process works for any modulo value.

5. Worked Sequence Analysis: Modulo-5 Counter

Analysing the full output sequence of a modulo-n counter is a common exam task. You need to trace each clock pulse, show the binary count, and identify the exact pulse at which the reset fires. The modulo-5 case is a good one to practise because 5 in binary is 101, which means the gate must detect two non-adjacent bits — a slightly trickier pattern than modulo-6.

Worked example: Tracing the Output Sequence of a Modulo-5 Counter

A 3-bit counter uses a NAND gate connected to $Q_2$ and $Q_0$ to drive an active-LOW reset pin. Trace the output sequence for eight clock pulses and confirm the modulo value.

1. $5_{10} = 101_2$, so $Q_2 = 1$, $Q_1 = 0$, $Q_0 = 1$ — The HIGH bits at count 5 are $Q_2$ and $Q_0$. Connecting these to a NAND gate is correct for an active-LOW reset.
2. Count 0: 000 — NAND inputs (0,0) → output HIGH, no reset Count 1: 001 — NAND inputs (0,1) → output HIGH, no reset Count 2: 010 — NAND inputs (0,0) → output HIGH, no reset Count 3: 011 — NAND inputs (0,1) → output HIGH, no reset Count 4: 100 — NAND inputs (1,0) → output HIGH, no reset — At every count from 0 to 4, at least one of $Q_2$ or $Q_0$ is LOW, so the NAND gate output stays HIGH and the reset pin is not activated.
3. Count 5: 101 — NAND inputs ($Q_2=1$, $Q_0=1$) → output LOW → reset pin activated → counter returns to 000 — Both $Q_2$ and $Q_0$ are HIGH simultaneously for the first time at count 5. The NAND gate output goes LOW, the active-LOW reset fires, and the counter is forced back to 000 immediately.
4. Sequence: 0 → 1 → 2 → 3 → 4 → (5: reset) → 0 → 1 → 2 → 3 → 4 → (5: reset) →... — The counter visits exactly 5 stable states (0 through 4) before resetting. State 5 is transient. This confirms modulo-5 behaviour.
5. No count from 0 to 4 has both $Q_2 = 1$ and $Q_0 = 1$ simultaneously. Verified in Step 2. — This check is essential in exam answers. If any earlier count also had both gate inputs HIGH, the counter would reset prematurely and the modulo value would be wrong.

Answer: The counter sequences through states 0, 1, 2, 3, 4 and resets on reaching 5. It is a modulo-5 counter. The NAND gate connected to $Q_2$ and $Q_0$ correctly drives the active-LOW reset.

6. Potential Pitfalls and Design Considerations

One subtlety worth examining is what happens when the binary representation of n contains only a single HIGH bit — for example, modulo-4 from a 3-bit counter. Count 4 is 100 in binary, so only $Q_2$ is HIGH. A single-input NAND gate is just a NOT gate, which would output LOW whenever $Q_2$ is HIGH. However, because the counter resets to 000 immediately at count 4, $Q_2$ returns to 0 and the reset is released before the next clock edge — so counts 5, 6, and 7 are never reached. The design works correctly in practice.

In practice, once the counter resets to 000, $Q_2$ returns to 0, the NOT/NAND output returns HIGH, and the reset is released — so the counter does work correctly as modulo-4. However, for exam purposes, the cleanest designs use counts whose binary form has at least two HIGH bits, because the AND/NAND gate then provides a unique detection condition that cannot be confused with any other count.

A second consideration is propagation delay. The gate takes a tiny but finite time to respond to the count reaching n. During that delay, the counter momentarily holds state n before the reset arrives. This transient is normally too brief to affect system behaviour, but it is worth mentioning in evaluation questions that ask you to assess the reliability of the design.

7. Exam Technique and Mark-Winning Strategies

AQA exam questions on modulo-n counters tend to follow a predictable pattern: you are given a counter circuit diagram, told the modulo value, and asked either to identify the gate connections or to trace the output sequence. Knowing the examiner's expectations at each stage will help you collect every available mark.

For longer 'evaluate' or 'discuss' questions, a strong answer will acknowledge the propagation delay as a limitation, note that the design works correctly for practical purposes because the transient at state n is negligibly brief, and conclude that the gate-and-reset-pin approach is a reliable and component-efficient method for implementing any modulo value from a standard binary counter.

Modulo-n counters bring together two core ideas from this topic: the sequential behaviour of a binary counter and the combinational logic of gate building blocks. Master the binary-conversion step and the active-level matching rule for the reset pin, and you have a reliable method for any modulo value the examiner can set.